1. Field of the Invention
The present invention relates to an analog-to-digital converter (ADC) using a sigma delta modulation technique. In particular, the present invention relates to an ADC using a sigma delta (SD) modulation technique in which the number of clock cycles required for each conversion is not constrained by the oversampling ratio, unlike conventional 1st order SD converters.
2. Discussion of the Related Art
In a conventional 1st order SD ADC, the number of clock cycles necessary for each conversion is proportional to the oversampling ratio (OSR), which is given by OSR=2N, where N is the number of bits in the digital output value. Thus, the conversion time doubles for each additional bit of resolution. To obtain a higher resolution without the exponential increase in conversion time, a higher-order SD converter may be used. However, such a SD ADC has a higher complexity and requires a greater converter area because of the higher-order decimation filters and the larger number of integrators required.
Many approaches aimed at overcoming the OSR constraint have been tried. For example, the article “A 16-bit, 150 uW, 1 kS/s ADC with hybrid incremental and cyclic conversion scheme” (“Rossi”), by L. Rossi et al., published in IEEE International Conference on Electronics, Circuits and Systems (ICECS 2009), Medina, Tunisia, Dec. 13-16, 2009, discloses a circuit that uses an SD ADC to obtain the most significant bits (MSBs) and which applies a non-SD ADC—in this case, a cyclic ADC—on the residue to obtain the least significant bits (LSBs) in the output value.
U.S. Pat. No. 5,936,562, entitled “High-speed Sigma Delta ADCs” to Brooks et al., filed on Jun. 6, 1997 and issued on Aug. 10, 1999, also discloses applying a non-SD ADC on the residue to obtain the LSBs in the output value.
U.S. Pat. No. 7,511,648, entitled “Integrating/SAR and Method with Low Integrator Swing and Low Complexity” (“Trifonov”), to D. Trifonov et al., discloses a hybrid approach that uses both SD modulation and non-SD techniques. In this case, the non-SD technique is a successive approximation register (SAR) technique. However, Trifinov's approach requires a control unit to implement the SAR algorithm, a multiply-by-2 circuit, and a complex circuit for combining the results of the SD and the non-SD conversions.